Comparison of ARMv8-A cores

This is a table of 64/32-bit ARMv8-A architecture cores, comparing microarchitectures which implement the AArch64 instruction set and mandatory or optional extensions of it. All chips of this type have a floating-point unit (FPU) that is better than that of older ARMv7 and NEON (SIMD) chips. Some of these chips have coprocessors, such as the AppliedMicro Helix that also includes cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

Table

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Company Core Released Decode Pipeline depth Out-of-order execution Branch prediction big.LITTLE role Execution ports Fab
(in nm)		 L1 cache
I.cache+D.cache
(in KiB)		 L2 cache L3 cache Core configurations DMIPS/MHz
ARM Holdings Cortex-A32 (32-bit) [1] ? LITTLE 28[2] 8–32 + 8–32 0–1 MiB No 1-4+
Cortex-A35[3] 2-wide[4] 8 No Yes LITTLE ? 28 / 16 / 14 8–64 + 8–64 0 / 128 KiB–1 MiB No 1–4+ 1.78
Cortex-A53[5] 2-wide 8 No Conditional+Indirect branch prediction big/LITTLE 2 28 / 20 / 16 / 14 8–64 + 8–64 128 KiB–2 MiB No 1–4+ 2.24
Cortex-A57 3-wide 15 Yes Two-level big 8 28 / 20 / 16[6] / 14 48 + 32 0.5–2 MiB No 1–4+ 4.6
Cortex-A72[7] 3-wide 15 Yes
5-wide dispatch 		Two-level big 8 28 / 16 48 + 32 0.5–4 MiB No 1–4+ 4.72
Cortex-A73[8] 2-wide 11–12 Yes
6-wide dispatch 		Two-level big 7 28 / 10 64 + 32/64 1–8 MiB No 1–4+ 4.8
Apple Inc. Cyclone[9] 6-wide[10] 16[10] Yes[10] ? No 9[10] 28[11] 64 + 64[10] 1 MiB[10] 4 MiB[10] 2[12] ?
Typhoon 6-wide[13] 16[13] Yes[13] ? No 20 64 + 64[10] 1 MiB[13] 4 MiB[10] 2, 3 (A8X) ?
Twister 6-wide[13] 16[13] Yes[13] ? No 16 / 14 64 + 64[13] 3 MiB[13] 4 MiB[13] 2 ?
Hurricane 6-wide 16 Yes ? "big" (in Apple A10 paired with "LITTLE" Zephyr cores e.g. Apple's own similar implementation) 16 64 + 64[14] 3 MiB[14] 4 MiB[14] 2 (+ 2× Zephyr) ?
Nvidia Denver[15][16] 2-wide hardware decoder,
up to 7-wide variable-length VLIW micro-ops 		13 Not if the hardware decoder is in use.
Can be provided by dynamic software translation into VLIW. 		Direct+Indirect branch predicton No 7 28 128 + 64 2 MiB No 2 ?
Denver 2[17] ? 13 ? ? "Super" Nvidia's own implementation ? 16 128+64 2 MiB No 2 ?
Cavium ThunderX 2-wide ? No No ? 28 78 + 32[18][19] 16 MiB[18][19] No 8–16, 24–48 2.0Ghz
AppliedMicro X-Gene 4-wide (XGene 1) 15 Yes ? ? ? 40 / 28 / 16[20] 32 + 32 (per core; write-through w/parity) 256 KiB shared per core pair (with ECC) XGene 1 – 8 MiB "hangs off of this coherent network";
XGene 2 – 2400 KiB combined in hierarchy (>2400 next version) 		8, 16, 64 4.2
Helix ? ? ? ? ? ? ? 40 / 28 32 + 32 (per core; write-through w/parity)[21] 256 KiB shared per core pair (with ECC) 1 MiB per core 2, 4, 8 ?
Broadcom Vulcan TBA 8-wide "4 μops"[22][23] "quad-threaded" ? ? Multi-level ? ? 16[24] 32 + 32 (data 8-way) 256 KiB (8-way) ? ?
Qualcomm Kryo 2016, Q1 ? ? Yes Two-level? "big" or "LITTLE" Qualcomm's own similar implementation ? 14[25] 32 + 32[26] 512 KiB–1 MiB No 2, 4 6.3
Samsung Mongoose[27] 2016, Q1 4-wide ? Yes[28] Two-level big 8 14 64 + 32 2 MiB[29] ? 4 ?
Company Core Released Decode Pipeline depth Out-of-order execution Branch prediction big.LITTLE role Execution ports Fab
(in nm)		 L1 cache
I.cache+D.cache
(in KiB)		 L2 cache L3 cache Core configurations DMIPS/MHz

As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

See also

References

  1. ↑ Frumusanu, Andrei (22 February 2016). "ARM Announces Cortex-A32 IoT and Embedded Processor". Anandtech.com. Retrieved 13 June 2016.
  2. ↑ "New Ultra-efficient ARM Cortex-A32 Processor Expands… - ARM". www.arm.com. Retrieved 2016-10-01.
  3. ↑ "Cortex-A35 Processor". ARM. ARM Ltd.
  4. ↑ http://anandtech.com/show/9769/arm-announces-cortex-a35
  5. ↑ "Cortex-A53 Processor". ARM. ARM Ltd.
  6. ↑ "TSMC Delivers First Fully Functional 16FinFET Networking Processor". TSMC. 25 September 2014. Retrieved 19 February 2015.
  7. ↑ Frumusanu, Andrei. "ARM Reveals Cortex-A72 Architecture Details". Anandtech. Retrieved 25 April 2015.
  8. ↑ Frumusanu, Andrei (29 May 2016). "The ARM Cortex A73 - Artemis Unveiled". Anandtech.com. Retrieved 31 May 2016.
  9. ↑ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: The Move to 64-bit". AnandTech. Retrieved 3 July 2014.
  10. 1 2 3 4 5 6 7 8 9 Lal Shimpi, Anand (31 March 2014). "Apple's Cyclone Microarchitecture Detailed". AnandTech. Retrieved 3 July 2014.
  11. ↑ Dixon-Warren, Sinjin (20 January 2014). "Samsung 28nm HKMG Inside the Apple A7". Chipworks. Retrieved 3 July 2014.
  12. ↑ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: A7 SoC Explained". AnandTech. Retrieved 3 July 2014.
  13. 1 2 3 4 5 6 7 8 9 10 Ho, Joshua; Smith, Ryan (2 Nov 2015). "The Apple iPhone 6s and iPhone 6s Plus Review". AnandTech. Retrieved 13 Feb 2016.
  14. 1 2 3 "Apple A10 Fusion". system-on-a-chip.specout.com. Retrieved 2016-10-01.
  15. ↑ Stam, Nick (11 August 2014). "Mile High Milestone: Tegra K1 "Denver" Will Be First 64-bit ARM Processor for Android". NVidia. Retrieved 11 August 2014.
  16. ↑ Gwennap, Linley. "Denver Uses Dynamic Translation to Outperform Mobile Rivals". The Linley Group. Retrieved 24 April 2015.
  17. ↑ Ho, Joshua (25 August 2016). "Hot Chips 2016: NVIDIA Discloses Tegra Parker Details". Anandtech. Retrieved 25 August 2016.
  18. 1 2 "64-bit Cortex Platform To Take On x86 Servers In The Cloud". electronic design. 5 June 2014. Retrieved 7 February 2015.
  19. 1 2 "ThunderX_CP™ Family of Workload Optimized Compute Processors" (PDF). Cavium. 2014. Retrieved 7 February 2015.
  20. ↑ Morgan, Timothy Prickett (12 August 2014). "Applied Micro Plots Out X-Gene ARM Server Future". Enterprisetech. Retrieved 9 October 2014.
  21. ↑ Ganesh T S (3 October 2014). "ARMv8 Goes Embedded with Applied Micro's HeliX SoCs". AnandTech. Retrieved 9 October 2014.
  22. ↑ https://hpcuserforum.com/presentations/santafe2014/Broadcom%20Monday%20night.pdf
  23. ↑ http://www.linleygroup.com/events/agenda.php?num=24&day=1
  24. ↑ "Broadcom Announces Server-Class ARMv8-A Multi-Core Processor Architecture". Broadcom. 15 October 2013. Retrieved 11 August 2014.
  25. ↑ "Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute". Qualcomm. 2 September 2015. Retrieved 6 September 2015.
  26. ↑ http://www.anandtech.com/show/9837/snapdragon-820-preview/
  27. ↑ http://www.anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu
  28. ↑ Frumusanu, Andrei. "Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU". Anandtech. Retrieved 26 November 2015.
  29. ↑ http://www.theregister.co.uk/2016/08/22/samsung_m1_core/
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