ARM Cortex-A53
| Designed by | ARM Holdings |
|---|---|
| Microarchitecture | ARMv8-A |
| Cores | 1–4 per cluster |
| L1 cache | 8–64 KB |
| L2 cache | 128 KB–2 MB |
The ARM Cortex-A53 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A53 is a superscalar processor capable of dual-issuing some instructions.[1] It is available as SIP core to licensees, and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration.
Overview
- 8-stage pipelined processor with 2-way superscalar, in-order execution pipeline
- DSP and NEON SIMD extensions are mandatory per core
- VFPv4 Floating Point Unit onboard (per core)
- Hardware virtualization support
- TrustZone security extensions
- 64-byte cache lines
- 10-entry L1 TLB, and 512-entry L2 TLB
- 4 Kb conditional branch predictor, 256-entry indirect branch predictor
See also
References
- ↑ "Cortex-A53 Processor". ARM Holdings. Retrieved 2015-11-08.
External links
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