High Bandwidth Memory

Cut through a graphics card that uses High Bandwidth Memory. See the TSVs.

High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked DRAM from AMD and Hynix. It is to be used in conjunction with high-performance graphics accelerators and network devices.^[1] The first devices to use HBM are the AMD Fiji GPUs.^[2][3]

High Bandwidth Memory has been adopted by JEDEC as an industry standard in October 2013.^[4] The second generation, HBM2, was accepted by JEDEC in January 2016.^[5]

Technology

HBM achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4 or GDDR5.^[6] This is achieved by stacking up to eight DRAM dies, including an optional base die with a memory controller, which are interconnected by through-silicon vias (TSV) and microbumps. The HBM technology is similar in principle but incompatible with the Hybrid Memory Cube interface developed by Micron Technology.^[7]

HBM memory bus is very wide in comparison to other DRAM memories such as DDR4 or GDDR5. An HBM stack of four DRAM dies (4-Hi) has two 128-bit channels per die for a total of 8 channels and a width of 1024 bits in total. A graphics card/GPU with four 4-Hi HBM stacks would therefore have a memory bus with a width of 4096 bits. In comparison, the bus width of GDDR memories is 32 bits, with 16 channels for a graphics card with a 512-bit memory interface.^[8] HBM will support up to 4GB per package.

Interface

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses a 500MHz differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128 bit data bus operating at DDR data rates. HBM supports transfer rates of 1 GT/s per pin (transferring 1 bit), yielding an overall package bandwidth of 128 GB/s.^[9]

HBM 2

The second generation of High Bandwidth Memory, HBM 2, also specifies up to 8 dies per stack and doubles pin transfer rates up to 2 GT/s. Retaining 1024-bit wide access, HBM2 is able to reach 256 GB/s memory bandwidth per package. The HBM2 spec allows up to 8GB per package. HBM2 is predicted to be especially useful for performance sensitive consumer applications such as virtual reality.^[10]

On January 19, 2016, Samsung announced early mass production of HBM2, at up to 4GB per stack.^[11][12] SK Hynix also announced availability of 4GB stacks in August 2016.^[13]

History

AMD Fiji, the first GPU to use HBM.

The development of High Bandwidth Memory began at AMD in 2008 to solve the problem of ever increasing power usage and form factor of computer memory. Amongst other things AMD developed procedures to solve the die stacking problems with a team led by Senior AMD Fellow Bryan Black. Partners from the memory industry (SK Hynix), interposer industry (UMC) and packaging industry (Amkor Technology and ASE) were obtained to help AMD realize their vision of HBM.^[14] High volume manufacturing began at a Hynix facility in Icheon, Korea in 2015.

HBM has been adopted as industry standard JESD235 by JEDEC as of October 2013 following a proposal by AMD and SK Hynix in 2010.^[4] The first chip utilizing HBM is AMD Fiji which was released in June 2015 powering the AMD Radeon R9 Fury X.^[15][2][16]

HBM2 was accepted by JEDEC as standard JESD235a in January 2016.^[5] The first GPU chip utilizing HBM2 is the Nvidia Tesla P100 which was officially announced in April 2016.^[17][18]

Future

At Hot Chips in August 2016 both Samsung and Hynix announced the next generation HBM memory technologies.^[19][20] Both companies announced high performance products expected to have increased density, increased bandwidth, and lower power. Samsung also announced a lower cost version of HBM under development targeting mass markets. Removing the buffer die and decreasing the number of TSVs lowers cost, though at the expense of a decreased overall bandwidth (200GB/s).

See also

• Stacked DRAM
• Chip stack multi-chip modules
• Hybrid Memory Cube stacked memory standard from Micron (2011)
• JEDEC Wide I/O, Wide I/O 2 (JESD229-2)^[21][22]

References

External links

• HIGH BANDWIDTH MEMORY (HBM) DRAM (JESD235), JEDEC, October 2013
• 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29 nm process and TSV. D.U Lee, SK hynix, ISSCC 2014 doi:10.1109/ISSCC.2014.6757501